The present invention relates to a controller for controlling an external storage or sub-memory unit such as a hard disk drive, a floppy disk drive, an optical disk drive and a cartridge magnetic tape drive employed in an information processing system and, more particularly, to an improvement in a data transfer control unit in such a memory controller.
An information processing system, which processes, manages and stores a great amount of data, includes one or more external storage or sub-memory units described above in addition to a main memory unit. A memory controller is thus required which intervenes between a host processor and the sub-memory unit to perform a data transfer operation therebetween. In general, such a memory controller includes an interface control unit for interfacing with the host processor, a buffer memory for temporarily storing data read from or to be written into the sub-memory unit, and a data transfer control unit for performing a data transfer operation between the interface control unit and the buffer memory. In accordance with requests from the host processor, the memory controller writes data from the host processor into the sub-memory unit and reads data from the sub-memory unit to the host processor.
The host processor often requires to obtain data that are the same as the data which were written into or read from the sub-memory unit by the previous request. Even in such a case, if the memory controller is constructed to perform the data read operation from the sub-memory unit whenever the access request is generated from the host processor, it takes a relatively long time to transfer the required data to the host processor. This is because the access speed of the sub-memory unit is slow.
In order to solve this problem, it has been proposed to apply a so-called cache memory technique to the memory controller for the sub-memory unit. Specifically, the memory controller is constructed to be connected with or to include a cache memory for storing a part of data written in the sub-memory unit and the data transfer control unit is added with a function of controlling the cache memory. Accordingly, if the cache memory stores data that are the same as the data required by the host processor, those data are read out of the cache memory and then transferred via the interface unit to the host processor. No data read operation from the sub-memory unit is thus required. On the other hand, in case where the cache memory does not store the data required by the host processor, the data read operation from the sub-memory unit is initiated. The data read from the sub-memory unit is first temporarily stored in the buffer memory. The data thus stored in the buffer memory is then transferred to the cache memory under the control of the data transfer control unit. Thereafter, the data read operation from the cache memory is initiated, so that the data is transferred to the interface unit from the cache memory and finally to the host processor.
Thus, the data transfer speed is improved remarkably in case of the cache memory storing the required data, but the data transfer speed is lowered extremely in the case of the cache memory not storing the required data since the data read out of the sub-memory unit is transferred from the buffer memory to the interface unit under the intervention of the cache memory. Moreover, when the host processor requires to write data into the sub-memory unit, that data is first stored into the cache memory from the interface unit and thereafter transferred to the buffer memory from the cache memory. The data write speed into the sub-memory unit is thereby lowered.